This invention relates to a low-voltage differential signaling (LVDS) buffer design that enables operation at current mode logic (CML) voltage levels.
LVDS and CML are two standards commonly used for differential signal transmission. These standards are especially common in the field of high-speed serial (HSS) interfaces. While each standard has its own advantages and disadvantages, LVDS is generally preferable to CML because it consumes less power due to its lower quiescent DC current. LVDS is also preferable to CML because its implementation has a more standard specification and is less vendor specific.
Ordinarily, it is difficult for an LVDS transceiver to DC couple to a CML transceiver because both of the transceivers would operate at different DC voltage levels. Thus, typically when coupling LVDS and CML transceivers, only AC coupling may be used.
AC coupling decouples or blocks the DC voltage values at the transmitter (TX) and receiver (RX) sides, respectively. AC coupling allows both the transmitter and receiver to operate at DC voltage levels which are optimal. However there is overhead required for AC coupling, such as coupling capacitors for blocking the DC voltage levels, and special signal encoding to prevent drifting of the DC voltage level. Accordingly, DC coupling may be preferable to AC coupling. It would therefore be desirable to design an LVDS transmitter which may be able to DC couple to a CML receiver.
Programmable logic devices (“PLDs”) are well known as shown, for example, by such references as Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, Jefferson et al. U.S. Pat. No. 6,215,326, and Ngai et al. U.S. Pat. No. 6,407,576. In general, a PLD is a general-purpose integrated circuit device that is programmable to perform any of a wide range of logic tasks. Rather than designing and building separate logic circuits for performing different logic tasks, general-purpose PLDs can be programmed in various different ways to perform those various logic tasks. Many manufacturers of electronic circuitry and systems find PLDs to be an advantageous way to provide various components of what they need to produce.
Typically, PLDs are designed with LVDS transceivers because of their high-speed, low-power consumption and versatility. While no one type of transceiver is ideally suited for every application, LVDS transceivers are used in PLDs in order to serve a wide customer base with different requirements. In order for the PLDs to serve additional customers that use CML transceivers, it would be highly desirable to provide an LVDS-like transceiver that would also be able to provide DC coupling to a CML transceiver.